Power connection problems typically are not identified until late in the design phase when full-chip layout-versus-schematic (LVS) check and/or full-chip power grid analysis (PGA), which includes electromigration (EM) and voltage (IR) drop evaluations, are performed. These problems usually have to be corrected, either manually or with various post-processing scripts, at each iteration of final chip assembly.
As a chip floor plan evolves over time, a chip power grid becomes susceptible to connectivity issues. A minor change in circuit placement, a circuit's reserved metal blockage, or a circuit's power image may result in new power distribution problems. Unfortunately, such issues are often not identified until full-chip physical design (PD) checks are performed. Then, rebuilding an existing chip power distribution network may even become necessary in order to resolve the new conflicts. However, complete re-implementation of full-chip power grid for designs that are already in controlled engineering change (EC) mode is usually not desired, as this action may result in changes that may require design re-qualifications beyond the original intended circuit's EC.
Pre-processing of design data is required for conventional PD checks. Both a logical and a physical netlist representing the full-chip hierarchy are constructed from the graphical design database. These are used as inputs for full-chip LVS or LVS-continuity (LVSC) based check. Both the logical and the physical chip netlists are typically very large and very time-consuming to produce. In addition to these netlists, full-chip PGA also needs more complete circuit and technology power characteristics to perform its checks.
Construction of the logical netlist is based on the connectivity information already existing in the chip floor plan. Connectivity information in the chip floor plan, which includes all power nets, is typically created automatically by a computer-aided process, which translates and imports the full-chip logical description (usually coded in a hardware description language) into the graphical chip floor plan in the physical design database.
Construction of the physical netlist is based on the actual implementation of the complete physical design hierarchy including all metallurgy and via structures for all power nets. For the full-chip power grid, power net connectivity is created automatically by the automated chip power router as part of its routing process.
The chip physical netlist also expects a complete full-chip power via structure. Power vias are usually created automatically by the same automated chip power router and based on the power net connectivity already existing in the routed power grid. The success of the power via generation step is highly dependent on the quality of the input power grid.
In addition to the chip power via generation process, advanced chip power routing methods also support personalization of the chip power grid on specific metal layers for selective circuits. Such personalization is performed after a full-chip power grid is created by an automated router. An effective personalization technique called “power pin extensions” is used to add power wiring continuity to the full-chip power grid for any power metal of any circuit. This technique allows design flexibility for the custom circuit's power grid while maintaining the overall robustness of the complete chip power distribution. Similar to the above power via generation process, the result of such personalization also depends on the quality of the input power grid, ideally with zero shorts or other errors between metal layers. It is therefore costly to wait until final full-chip checks to perform needed corrections, and then to repeat the whole routing process.
Finally, after translating the design data into netlists to be used as inputs for checking, the actual full-chip checks are themselves very memory- and run-time intensive. As large chips such as chip multiprocessor (CMP) designs continue to grow in demand and grow to contain more than one billion transistors, the speed of these full-chip checking processes is increasingly a major concern. These checking jobs not only take a long time to complete, but also when they complete, additional analysis is still necessary to identify the actual source of problems. For example, a full-chip LVS or LVSC check typically finds the first short and then stops. An extra function is then required to trace the approximate location of the short. After this short is fixed, a repeat of LVS or LVSC is needed to find the next problem.
Some chip distribution network contains power metals that add no value to the complete chip power distribution network. These metals typically are created by the automated power router for certain types of voltage region and macro placement boundary conditions. They typically are very short wires and are discovered only by chip EM or IR-drop analysis. For instance, if large IR-drops are discovered because of truncation at macro cell boundaries, the underpowered rails should be removed from the network to enable a more efficient solution. If such problems are discovered too late in the design cycle, less ideal solutions, such as those requiring extra wiring resources, may have to be implemented.